Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks

TL;DR

This paper presents a fast, end-to-end simulation framework for many-core RISC-V based SDR transceivers, enabling rapid performance analysis of 5G physical layer functions in realistic wireless environments.

Contribution

It introduces a static binary translation simulator with an approximate hardware timing model, significantly accelerating SDR hardware validation and performance exploration.

Findings

Simulation of 5G OFDM detection in 9.5 seconds to 3 minutes

Achieves 73-121x speedup with 128-thread parallelization

Over 1000x faster than traditional RTL simulation

Abstract

The fast-rising demand for wireless bandwidth requires rapid evolution of high-performance baseband processing infrastructure. Programmable many-core processors for software-defined radio (SDR) have emerged as high-performance baseband processing engines, offering the flexibility required to capture evolving wireless standards and technologies. This trend must be supported by a design framework enabling functional validation and end-to-end performance analysis of SDR hardware within realistic radio environment models. We propose a static binary translation based simulator augmented with a fast, approximate timing model of the hardware and coupled to wireless channel models to simulate the most performance-critical physical layer functions implemented in software on a many (1024) RISC-V cores cluster customized for SDR. Our framework simulates the detection of a 5G OFDM-symbol on a server-class processor in 9.5s-3min, on a single thread, depending on the input MIMO size (three orders of magnitude faster than RTL simulation). The simulation is easily parallelized to 128 threads with 73-121x speedup compared to a single thread.