Resource-Efficient Synthesis of Sparse Quantum States

TL;DR

This paper introduces a resource-efficient quantum state synthesis algorithm that minimizes circuit depth, ancilla, and non-Clifford gates for sparse states, crucial for fault-tolerant quantum computing.

Contribution

It presents a novel algorithm for synthesizing sparse quantum states with linear resource scaling, including a new tree-based W-state synthesis and a minimal-depth reversible permutation circuit.

Findings

Circuit depth, ancilla count, and non-Clifford gates scale linearly with sparsity.

A new tree-based approach efficiently synthesizes generalized W-states.

A parallel Gauss-Jordan elimination method minimizes circuit complexity.

Abstract

Preparing a quantum circuit that implements a given sparse state is an important building block that is necessary for many different quantum algorithms. In the context of fault-tolerant quantum computing, the so-called non-Clifford gates are much more expensive to perform than the Clifford ones. We hence provide an algorithm for synthesizing sparse quantum states with a special care for quantum resources. The circuit depth, ancilla count, and crucially non-Clifford count of the circuit produced by the algorithm are all linear in the sparsity. We conjecture that the non-Clifford count complexity is tight, and show a weakened version of this claim. The first key component of the algorithm is the synthesis of a generalized W-state. We provide a tree-based circuit construction approach, and the relationship between the tree's structure and the circuit's complexity. The second key component is a classical reversible circuit implementing a permutation that maps the basis states of the W-state to those of the sparse quantum state. We reduce this problem to the diagonalization of a binary matrix, using a specific set of elementary matrix operations corresponding to the classical reversible gates. We then solve this problem using a new version of Gauss-Jordan elimination, that minimizes the circuit complexities including circuit depth using parallel elimination steps.