ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs

TL;DR

ECOLogic introduces a hybrid ASIC-eFPGA architecture with a scoring framework to enable secure, updatable, and resource-efficient systems, significantly reducing power consumption and carbon footprint while maintaining high performance.

Contribution

The paper presents ECOLogic, a novel hybrid design integrating lightweight eFPGA within ASICs, guided by ECOScore for optimized partitioning, enhancing reconfigurability, security, and sustainability.

Findings

Achieves 90% of ASIC performance at 2 GHz

Reduces power consumption by 480 times compared to FPGA-only systems

Cuts deployment carbon footprint by 99.7%

Abstract

Traditional hardware platforms - ASICs and FPGAs - offer competing trade-offs among performance, flexibility, and sustainability. ASICs provide high efficiency but are inflexible post-fabrication, require costly re-spins for updates, and expose IPs to piracy risks. FPGAs offer reconfigurability and reuse, yet suffer from substantial area, power, and performance overheads, resulting in higher carbon footprints. We present ECOLogic, a hybrid design paradigm that embeds lightweight eFPGA fabric within ASICs to enable secure, updatable, and resource-aware computation. Central to this architecture is ECOScore, a quantitative scoring framework that evaluates IPs based on adaptability, piracy threat, performance tolerance, and resource fit to guide RTL partitioning. Evaluated across six diverse SoC modules, ECOLogic retains an average of 90 percent ASIC-level performance (up to 2 GHz), achieves 9.8 ns timing slack (versus 5.1 ns in FPGA), and reduces power by 480 times on average. Moreover, sustainability analysis shows a 99.7 percent reduction in deployment carbon footprint and 300 to 500 times lower emissions relative to FPGA-only implementations. These results position ECOLogic as a high-performance, secure, and environmentally sustainable solution for next-generation reconfigurable systems.