Moveless: Minimizing Overhead on QCCDs via Versatile Execution and Low Excess Shuttling

TL;DR

This paper introduces Moveless, a specialized compiler for quantum error correction circuits on QCCD hardware that reduces overhead by exploiting circuit structure, resulting in faster execution and significantly lower logical error rates.

Contribution

The paper presents a novel compilation scheme tailored for QEC circuits on QCCD hardware, optimizing qubit shuttling and execution order to minimize errors and improve performance.

Findings

QEC circuits compiled with Moveless are 3.38x faster on average.

Logical error rates improve by up to two orders of magnitude.

The approach exploits circuit regularity and hardware constraints for efficiency.

Abstract

One of the most promising paths towards large scale fault tolerant quantum computation is the use of quantum error correcting stabilizer codes. Just like every other quantum circuit, these codes must be compiled to hardware in a way to minimize the total physical error introduced into the system, for example either due to high latency execution or excessive gates to meet connectivity limitations of the target hardware. However, unlike arbitrary quantum circuits, all syndrome extraction circuits have several common properties, for example they have a bipartite connectivity graph, consist only of commuting subcircuits, among other properties. For the most part, compilation methods have aimed at being generic, able to map any input circuit into executables on the hardware, and therefore cannot appropriately exploit these properties and result in executables which have higher physical error. In the case of modular trapped ion systems, specifically QCCDs, this corresponds to the insertion of excessive shuttling operations necessary to realize arbitrary qubit interactions. We propose a compilation scheme explicitly tailored for the structural regularity of QEC circuits based on several key observations: 1. only ancilla or data (but not both) should be shuttled, 2. stabilizers can be executed in any order meaning we can dynamically modify circuit execution on a per-cycle basis 3. ancilla are indistinguishable meaning any can be selected to begin a stabilizer measurement and retain a fixed-point mapping between cycles, and 4. QCCD hardware limits the number of parallel operations equal to the number traps in the system, meaning fewer ancilla are necessary and can be reused. Our resulting compiler, leads to QEC circuits which are on average 3.38x faster to execute, and lead to up to two orders of magnitude of improvement in logical error rates with realistic physical error rates.