Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems

TL;DR

Rhea is a comprehensive framework that simplifies the design and validation of RTL cache-coherent memory subsystems, combining configurable RTL generation with hybrid simulation for realistic system testing.

Contribution

Rhea introduces an integrated approach for rapid RTL cache-coherent memory subsystem design and validation using configurable RTL generation and hybrid simulation with gem5 and Verilator.

Findings

Supports various cache architectures and core counts.

Achieves realistic validation with moderate simulation overhead.

Demonstrates scalability and effectiveness in multi-core scenarios.

Abstract

Designing and validating efficient cache-coherent memory subsystems is a critical yet complex task in the development of modern multi-core system-on-chip architectures. Rhea is a unified framework that streamlines the design and system-level validation of RTL cache-coherent memory subsystems. On the design side, Rhea generates synthesizable, highly configurable RTL supporting various architectural parameters. On the validation side, Rhea integrates Verilator's cycle-accurate RTL simulation with gem5's full-system simulation, allowing realistic workloads and operating systems to run alongside the actual RTL under test. We apply Rhea to design MSI-based RTL memory subsystems with one and two levels of private caches and scaling up to sixteen cores. Their evaluation with 22 applications from state-of-the-art benchmark suites shows intermediate performance relative to gem5 Ruby's MI and MOESI models. The hybrid gem5-Verilator co-simulation flow incurs a moderate simulation overhead, up to 2.7 times compared to gem5 MI, but achieves higher fidelity by simulating real RTL hardware. This overhead decreases with scale, down to 1.6 times in sixteen-core scenarios. These results demonstrate Rhea's effectiveness and scalability in enabling fast development of RTL cache-coherent memory subsystem designs.