SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation

TL;DR

This paper presents SAGE-HLS, a specialized fine-tuned language model for high-level synthesis code generation, addressing dataset scarcity and improving synthesis success and correctness in hardware design automation.

Contribution

Introduction of SAGE-HLS, the first fine-tuned LLM for HLS code generation, with dataset creation, AST-guided fine-tuning, and a semi-automated evaluation framework.

Findings

Near 100% code synthesizability success rate

75% functional correctness success rate

Effective AST-guided fine-tuning strategy

Abstract

In today's rapidly evolving field of electronic design automation (EDA), the complexity of hardware designs is increasing, necessitating more sophisticated automation solutions. High-level synthesis (HLS), as a pivotal solution, automates hardware designs from high-level abstractions (e.g., C/C++). However, it faces significant challenges, particularly in design space exploration and optimization. While large language models (LLMs) have shown notable capabilities in code generation, their application to HLS has been limited due to the scarcity of (publicly) available HLS code datasets. Hence, research in this domain has primarily focused on techniques such as prompt engineering and retrieval-augmented generation (RAG). To overcome this limitation, this paper introduces SAGE-HLS, the first-of-its-kind fine-tuned LLM specifically for HLS code generation. Our method includes three key advancements: (i) We implement Verilog-to-C/C++ porting, converting verified and synthesizable Verilog codes into corresponding C, creating a dataset of 16.7K HLS codes; (ii) We implement a fine-tuning strategy, which is based on instruction prompting to code generation guided by abstract syntax tree (AST); (iii) We develop a semi-automated evaluation framework using VerilogEval to assess the functionality of the generated HLS code. Our experiments show that SAGE-HLS, fined-tuned on the QwenCoder (2.5) 7B model, achieves a near 100% success rate in code synthesizability and a 75% success rate in functional correctness.