Thermal-Aware 3D Design for Side-Channel Information Leakage

TL;DR

This paper introduces a thermal-aware 3D design approach that proactively conceals sensitive on-chip activities and reduces side-channel vulnerabilities by leveraging 3D integration and dynamic activity pattern generation.

Contribution

It presents a novel method combining 3D integration with runtime algorithms to minimize thermal side-channel leakage while maintaining low power dissipation.

Findings

Reduces Side channel vulnerability Factor (SVF) below 0.05.

Reduces Spatial Thermal Side-channel Factor (STSF) below 0.59.

Effectively conceals critical activities in functional layers.

Abstract

Side-channel attacks are important security challenges as they reveal sensitive information about on-chip activities. Among such attacks, the thermal side-channel has been shown to disclose the activities of key functional blocks and even encryption keys. This paper proposes a novel approach to proactively conceal critical activities in the functional layers while minimizing the power dissipation by (i) leveraging inherent characteristics of 3D integration to protect from side-channel attacks and (ii) dynamically generating custom activity patterns to match the activity to be concealed in the functional layers. Experimental analysis shows that 3D technology combined with the proposed run-time algorithm effectively reduces the Side channel vulnerability Factor (SVF) below 0.05 and the Spatial Thermal Side-channel Factor (STSF) below 0.59.