GSIM: Accelerating RTL Simulation for Large-Scale Designs

TL;DR

GSIM is a novel RTL simulator that significantly accelerates large-scale hardware design simulations by optimizing computation overhead factors, achieving up to 20x speedup over existing tools like Verilator.

Contribution

This work introduces GSIM, a new RTL simulation approach with techniques at multiple levels to enhance simulation speed for complex designs.

Findings

GSIM successfully simulates XiangShan, a large RISC-V processor.

GSIM achieves 7.34x speedup over Verilator for Linux boot on XiangShan.

GSIM attains 19.94x speedup for CoreMark on Rocket.

Abstract

Register Transfer Level (RTL) simulation is widely used in design space exploration, verification, debugging, and preliminary performance evaluation for hardware design. Among various RTL simulation approaches, software simulation is the most commonly used due to its flexibility, low cost, and ease of debugging. However, the slow simulation of complex designs has become the bottleneck in design flow. In this work, we explore the sources of computation overhead of RTL simulation and conclude them into four factors. To optimize these factors, we propose several techniques at the supernode level, node level, and bit level. Finally, we implement these techniques in a novel RTL simulator GSIM. GSIM succeeds in simulating XiangShan, the state-of-the-art open-source RISC-V processor. Besides, compared to Verilator, GSIM can achieve speedup of 7.34x for booting Linux on XiangShan, and 19.94x for running CoreMark on Rocket.