Towards Efficient Verification of Computation in Quantum Devices
Keren Li, Peng Yan, Hanru Jiang, Nengkun Yu

TL;DR
This paper introduces a scalable verification algorithm for quantum devices that leverages their structural properties, significantly reducing verification time and demonstrating practical effectiveness on IBM quantum hardware.
Contribution
It presents a novel, efficient verification method based on the layered circuit model, improving over traditional exponential approaches by exploiting circuit structure.
Findings
Verification time scales as O(d^2 t log(n/δ))
Algorithm successfully reconstructs quantum circuits with high probability
Validated on IBM quantum cloud, showing practical applicability
Abstract
Designing quantum processors is a complex task that demands advanced verification methods to ensure their correct functionality. However, traditional methods of comprehensively verifying quantum devices, such as quantum process tomography, face significant limitations because of the exponential growth in computational resources. These limitations arise from treating the system as a black box and ignoring its design structure. Consequently, new testing methods must be developed considering the design structure. In this paper, we investigate the structure of computations on the hardware, focusing on the layered interruptible quantum circuit model and designing a scalable algorithm to verify it comprehensively. Specifically, for a given quantum hardware that claims to process an unknown qubit layer circuit via a finite set of quantum gates, our method completely reconstructs the…
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Complexity and Algorithms in Graphs · Radiation Effects in Electronics
