HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions
Jing Wang, Shang Liu, Yao Lu, Zhiyao Xie

TL;DR
HLSDebugger leverages a large labeled dataset and an encoder-decoder LLM to automate bug detection and correction in HLS code, surpassing GPT-4 in accuracy and efficiency.
Contribution
This work introduces HLSDebugger, a novel LLM-based framework with a large dataset for automated HLS bug identification and correction, addressing key challenges in hardware debugging.
Findings
HLSDebugger outperforms GPT-4 in bug identification.
HLSDebugger achieves over 3x improvement in bug correction accuracy.
The dataset contains 300K labeled HLS logic bug samples.
Abstract
High-level synthesis (HLS) accelerates hardware design by enabling the automatic translation of high-level descriptions into efficient hardware implementations. However, debugging HLS code is a challenging and labor-intensive task, especially for novice circuit designers or software engineers without sufficient hardware domain knowledge. The recent emergence of Large Language Models (LLMs) is promising in automating the HLS debugging process. Despite the great potential, three key challenges persist when applying LLMs to HLS logic debugging: 1) High-quality circuit data for training LLMs is scarce, posing a significant challenge. 2) Debugging logic bugs in hardware is inherently more complex than identifying software bugs with existing golden test cases. 3) The absence of reliable test cases requires multi-tasking solutions, performing both bug identification and correction. complicates…
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