Large-scale characterization of Single-Hole Transistors in 22-nm FDSOI CMOS Technology

TL;DR

This paper demonstrates the integration of 384 silicon quantum dots with classical electronics on a 22-nm FDSOI CMOS chip at cryogenic temperatures, addressing scaling challenges in quantum processor development.

Contribution

It presents the first large-scale monolithic integration of quantum dots with CMOS electronics in a 22-nm process, linking device dimensions to quantum dot performance.

Findings

Successful integration of 384 quantum dots with electronics

Automated routines for quantum dot parameter extraction

Insights into device dimension effects on quantum dot yield and noise

Abstract

State-of-the-art quantum processors have recently grown to reach 100s of physical qubits. As the number of qubits continues to grow, new challenges associated with scaling arise, such as device variability reduction and integration with cryogenic electronics for I/O management. Spin qubits in silicon quantum dots provide a platform where these problems may be mitigated, having demonstrated high control and readout fidelities and compatibility with large-scale manufacturing techniques of the semiconductor industry. Here, we demonstrate the monolithic integration of 384 p-type quantum dots, each embedded in a silicon transistor, with on-chip digital and analog electronics, all operating at deep cryogenic temperatures. The chip is fabricated using 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. We extract key quantum dot parameters by fast readout and automated machine learning routines to determine the link between device dimensions and quantum dot yield, variability, and charge noise figures. Overall, our results demonstrate a path to monolithic integration of quantum and classical electronics at scale.