Optimization and Synthesis of Quantum Circuits with Global Gates

TL;DR

This paper presents a novel algorithm that optimizes quantum circuit synthesis by leveraging global gates specific to ion trap hardware, reducing the number of entangling operations needed.

Contribution

The work introduces a ZX-calculus-based algorithm for compiling quantum circuits into global gate-based circuits, optimizing entangling gate count for ion trap quantum computers.

Findings

Improves circuit performance on ion trap hardware

Reduces the number of global entangling gates needed

Outperforms naive and Qiskit optimizer approaches

Abstract

Compiling quantum circuits to account for hardware restrictions is an essential part of the quantum computing stack. Circuit compilation allows us to adapt algorithm descriptions into a sequence of operations supported by real quantum hardware, and has the potential to significantly improve their performance when optimization techniques are added to the process. One such optimization technique is reducing the number of quantum gates that are needed to execute a circuit. For instance, methods for reducing the number of non-Clifford gates or CNOT gates from a circuit is an extensive research area that has gathered significant interest over the years. For certain hardware platforms such as ion trap quantum computers, we can leverage some of their special properties to further reduce the cost of executing a quantum circuit in them. In this work we use global interactions, such as the Global M{\o}lmer-S{\o}rensen gate present in ion trap hardware, to optimize and synthesize quantum circuits. We design and implement an algorithm that is able to compile an arbitrary quantum circuit into another circuit that uses global gates as the entangling operation, while optimizing the number of global interactions needed. The algorithm is based on the ZX-calculus and uses an specialized circuit extraction routine that groups entangling gates into Global M{\o}lmer-S{\o}rensen gates. We benchmark the algorithm in a variety of circuits, and show how it improves their performance under state-of-the-art hardware considerations in comparison to a naive algorithm and the Qiskit optimizer.