A Wide-Input 0.25 um BCD LDO with Dual-Stage Amplifier and Active Ripple Cancellation for High PSRR and Fast Transient Response
Yi Zhang, Zhuolong Chen, Zhenghao Xu, Yujin He

TL;DR
This paper introduces a wide-input BCD LDO with dual-stage amplification and active ripple cancellation, achieving high PSRR and fast transient response suitable for high-performance SoCs and portable electronics.
Contribution
It presents a novel wide-input LDO architecture with active ripple cancellation and adaptive fast feedback, improving PSRR and transient response simultaneously.
Findings
Achieves -75 dB low-frequency PSRR
Maintains output droop under 0.65 V during load steps
Reaches recovery within 16 microseconds
Abstract
Demand for on-chip low-dropout regulators (LDOs) with both high power-supply rejection ratio (PSRR) and fast transient response is growing as system-on-chip (SoC) integration increases. However, conventional LDO architectures face difficulty achieving these performance metrics simultaneously over wide input voltage ranges. This paper presents a wide-input linear regulator implemented in 0.25 um BCD technology that attains high PSRR and swift load-transient performance while maintaining low quiescent current. The proposed LDO employs a dual-stage error amplifier architecture and active ripple cancellation along both the power path and the error amplifier's supply to significantly enhance PSRR across frequency. An adaptive fast feedback branch together with an on-chip frequency compensation network is introduced to accelerate transient response without compromising stability. A two-stage…
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