Target Circuit Matching in Large-Scale Netlists using GNN-Based Region Prediction

TL;DR

This paper introduces a GNN-based method for efficient subgraph matching in large-scale circuits, improving accuracy and scalability over traditional and existing deep learning approaches.

Contribution

It presents a novel GNN-based region prediction technique that captures global subgraph information and enhances efficiency in large circuit matching tasks.

Findings

Significantly faster than existing methods.

More accurate in predicting target regions.

Effective for large-scale circuit matching.

Abstract

Subgraph matching plays an important role in electronic design automation (EDA) and circuit verification. Traditional rule-based methods have limitations in generalizing to arbitrary target circuits. Furthermore, node-to-node matching approaches tend to be computationally inefficient, particularly for large-scale circuits. Deep learning methods have emerged as a potential solution to address these challenges, but existing models fail to efficiently capture global subgraph embeddings or rely on inefficient matching matrices, which limits their effectiveness for large circuits. In this paper, we propose an efficient graph matching approach that utilizes Graph Neural Networks (GNNs) to predict regions of high probability for containing the target circuit. Specifically, we construct various negative samples to enable GNNs to accurately learn the presence of target circuits and develop an approach to directly extracting subgraph embeddings from the entire circuit, which captures global subgraph information and addresses the inefficiency of applying GNNs to all candidate subgraphs. Extensive experiments demonstrate that our approach significantly outperforms existing methods in terms of time efficiency and target region prediction, offering a scalable and effective solution for subgraph matching in large-scale circuits.