Towards System-Level Quantum-Accelerator Integration

TL;DR

This paper proposes a system-level architecture for integrating quantum accelerators with classical systems, emphasizing low-latency, real-time interaction, and robust resource management, validated through emulation and FPGA simulations.

Contribution

It introduces a quantum systems architecture with a Quantum Abstraction Layer for real-time quantum-classical integration, validated via virtual QPU models and multi-architecture emulation.

Findings

Validated architecture through functional emulation on x86_64, ARM64, RISC-V

Demonstrated timing-accurate FPGA-based simulations

Provided a blueprint for low-latency quantum-classical orchestration

Abstract

Quantum computers are often treated as experimental add-ons that are loosely coupled to classical infrastructure through high-level interpreted languages and cloud-like orchestration. However, future deployments in both, high-performance computing (HPC) and embedded environments, will demand tighter integration for lower latencies, stronger determinism, and architectural consistency, as well as to implement error correction and other tasks that require tight quantum-classical interaction as generically as possible. We propose a vertically integrated quantum systems architecture that treats quantum accelerators and processing units as peripheral system components. A central element is the Quantum Abstraction Layer (QAL) at operating system kernel level. It aims at real-time, low-latency, and high-throughput interaction between quantum and classical resources, as well as robust low-level quantum operations scheduling and generic resource management. It can serve as blueprint for orchestration of low-level computational components "around" a QPU (and inside a quantum computer), and across different modalities. We present first results towards such an integrated architecture, including a virtual QPU model based on QEMU. The architecture is validated through functional emulation on three base architectures (x86_64, ARM64, and RISC-V), and timing-accurate FPGA-based simulations. This allows for a realistic evaluation of hybrid system performance and quantum advantage scenarios. Our work lays the ground for a system-level co-design methodology tailored for the next generation of quantum-classical computing.