Explicit Sign-Magnitude Encoders Enable Power-Efficient Multipliers

TL;DR

This paper introduces a sign-magnitude encoding approach for fixed point multipliers that significantly reduces power consumption, especially for AI workloads with zero-centered inputs, by optimizing the multiplier design and synthesis process.

Contribution

It proposes a novel encoder-based decomposition method for multipliers that enhances power efficiency while maintaining circuit logic equivalence.

Findings

Up to 12.9% lower switching activity with sign-magnitude encoding.

Power savings up to 33% for specific input ranges.

Additional 5-10% efficiency gains with switching-activity-driven synthesis.

Abstract

This work presents a method to maximize power-efficiency of fixed point multiplier units by decomposing them into sub-components. First, an encoder block converts the operands from a two's complement to a sign magnitude representation, followed by a multiplier module which performs the compute operation and outputs the resulting value in the original format. This allows to leverage the power-efficiency of the Sign Magnitude encoding for the multiplication. To ensure the computing format is not altered, those two components are synthesized and optimized separately. Our method leads to significant power savings for input values centered around zero, as commonly encountered in AI workloads. Under a realistic input stream with values normally distributed with a standard deviation of 3.0, post-synthesis simulations of the 4-bit multiplier design show up to 12.9% lower switching activity compared to synthesis without decomposition. Those gains are achieved while ensuring compliance into any production-ready system as the overall circuit stays logic-equivalent. With the compliance lifted and a slightly smaller input range of -7 to +7, switching activity reductions can reach up to 33%. Additionally, we demonstrate that synthesis optimization methods based on switching-activity-driven design space exploration can yield a further 5-10% improvement in power-efficiency compared to a power agnostic approach.