Designing High-Performance and Thermally Feasible Multi-Chiplet Architectures enabled by Non-bendable Glass Interposer
Harsh Sharma, Janardhan Rao Doppa, Umit Y. Ogras, Partha Pratim Pande

TL;DR
This paper presents a co-optimization framework for multi-chiplet architectures with glass interposers, addressing warpage challenges to improve performance, reduce power, and ensure reliability in large-scale systems.
Contribution
It introduces a novel design framework that combines architecture and packaging optimization to mitigate warpage and enhance performance in glass interposer-based multi-chiplet systems.
Findings
Achieves up to 64.7% performance improvement.
Reduces power consumption by 40%.
Enables scalable, reliable multi-chiplet architectures.
Abstract
Multi-chiplet architectures enabled by glass interposer offer superior electrical performance, enable higher bus widths due to reduced crosstalk, and have lower capacitance in the redistribution layer than current silicon interposer-based systems. These advantages result in lower energy per bit, higher communication frequencies, and extended interconnect range. However, deformation of the package (warpage) in glass interposer-based systems becomes a critical challenge as system size increases, leading to severe mechanical stress and reliability concerns. Beyond a certain size, conventional packaging techniques fail to manage warpage effectively, necessitating new approaches to mitigate warpage induced bending with scalable performance for glass interposer based multi-chiplet systems. To address these inter-twined challenges, we propose a thermal-, warpage-, and performance-aware design…
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Taxonomy
TopicsSemiconductor Lasers and Optical Devices · 3D IC and TSV technologies · Nanofabrication and Lithography Techniques
