Readout electronics for low occupancy High-Pressure Gas TPCs

TL;DR

This paper presents a cost-effective FPGA-based readout electronics system for high-pressure gas TPCs used in neutrino experiments, demonstrating successful operation and identifying areas for further improvement.

Contribution

The paper introduces a novel, low-cost FPGA-based readout solution optimized for high-pressure gas TPCs, suitable for large-scale neutrino detectors like DUNE.

Findings

Successfully read out ~10,000 channels at Fermilab

Low noise performance achieved in tests

System can meet detector needs at reduced cost

Abstract

HPgTPCs have benefits such as low energy threshold, magnetisability, and 4$\pi$ acceptance, making them ideal for neutrino experiments such as DUNE. We present the design of an FPGA-based solution optimised for ND-GAr, which is part of the Phase-II more capable near detector for DUNE. These electronics reduce the cost significantly compared to using collider readout electronics which are typically designed for much higher occupancy and therefore, for example, need much larger numbers of FPGAs and power per channel. We demonstrate the performance of our electronics with the TOAD at Fermilab in the US at a range of pressures and gas mixtures up to 4.5barA, reading out ~10000 channels from a multi-wire proportional chamber. The operation took place between April and July of 2024. We measure the noise characteristics of the system to be sufficiently low and we identify sources of noise that can be further mitigated in the next iteration. We also note that the cooling scheme used in the test requires improvement before full-scale deployment. Despite these necessary improvements, we show that the system can fulfil the needs of a HPgTPC for a fraction of the price of collider readout electronics.