Learning from Scratch: Structurally-masked Transformer for Next Generation Lib-free Simulation

TL;DR

This paper introduces a neural network framework that predicts power and timing in digital circuits with high accuracy, using waveform and delay estimation models conditioned on netlist parameters, surpassing traditional methods.

Contribution

It presents the first netlist-aware, language-based neural network for standard cells, employing a hybrid CNN-Transformer architecture for precise, scalable timing and power prediction.

Findings

Achieves SPICE-level accuracy with RMSE below 0.0098

Effectively models intrinsic and coupling delays without simplification

Provides a scalable neural alternative to conventional tools

Abstract

This paper proposes a neural framework for power and timing prediction of multi-stage data path, distinguishing itself from traditional lib-based analytical methods dependent on driver characterization and load simplifications. To the best of our knowledge, this is the first language-based, netlist-aware neural network designed explicitly for standard cells. Our approach employs two pre-trained neural models of waveform prediction and delay estimation that directly infer transient waveforms and propagation delays from SPICE netlists, conditioned on critical physical parameters such as load capacitance, input slew, and gate size. This method accurately captures both intrinsic and coupling-induced delay effects without requiring simplification or interpolation. For multi-stage timing prediction, we implement a recursive propagation strategy where predicted waveforms from each stage feed into subsequent stages, cumulatively capturing delays across the logic chain. This approach ensures precise timing alignment and complete waveform visibility throughout complex signal pathways. The waveform prediction utilizes a hybrid CNN-Transformer architecture with netlist-aware node-level encoding, addressing traditional Transformers' fixed input dimensionality constraints. Additionally, specialized subnetworks separately handle primary delay estimation and crosstalk correction. Experimental results demonstrate SPICE-level accuracy, consistently achieving RMSE below 0.0098 across diverse industrial circuits. The proposed framework provides a scalable, structurally adaptable neural alternative to conventional power and timing engines, demonstrating high fidelity to physical circuit behaviors.