Spintronic Bayesian Hardware Driven by Stochastic Magnetic Domain Wall Dynamics

TL;DR

This paper introduces a magnetic probabilistic computing platform using spintronic devices based on magnetic domain wall dynamics, enabling efficient uncertainty-aware AI inference with significant improvements over CMOS-based systems.

Contribution

It presents a novel hardware platform leveraging intrinsic magnetic stochasticity for probabilistic AI, demonstrating scalable, energy-efficient Bayesian neural network inference.

Findings

Achieves seven orders of magnitude improvement in figure of merit over CMOS

Enables fully electrical, tunable probabilistic functionality at device level

Demonstrates effective CIFAR-10 classification with Bayesian neural networks

Abstract

As artificial intelligence (AI) advances into diverse applications, ensuring reliability of AI models is increasingly critical. Conventional neural networks offer strong predictive capabilities but produce deterministic outputs without inherent uncertainty estimation, limiting their reliability in safety-critical domains. Probabilistic neural networks (PNNs), which introduce randomness, have emerged as a powerful approach for enabling intrinsic uncertainty quantification. However, traditional CMOS architectures are inherently designed for deterministic operation and actively suppress intrinsic randomness. This poses a fundamental challenge for implementing PNNs, as probabilistic processing introduces significant computational overhead. To address this challenge, we introduce a Magnetic Probabilistic Computing (MPC) platform-an energy-efficient, scalable hardware accelerator that leverages intrinsic magnetic stochasticity for uncertainty-aware computing. This physics-driven strategy utilizes spintronic systems based on magnetic domain walls (DWs) and their dynamics to establish a new paradigm of physical probabilistic computing for AI. The MPC platform integrates three key mechanisms: thermally induced DW stochasticity, voltage controlled magnetic anisotropy (VCMA), and tunneling magnetoresistance (TMR), enabling fully electrical and tunable probabilistic functionality at the device level. As a representative demonstration, we implement a Bayesian Neural Network (BNN) inference structure and validate its functionality on CIFAR-10 classification tasks. Compared to standard 28nm CMOS implementations, our approach achieves a seven orders of magnitude improvement in the overall figure of merit, with substantial gains in area efficiency, energy consumption, and speed. These results underscore the MPC platform's potential to enable reliable and trustworthy physical AI systems.