On-chip stencil lithography for superconducting qubits

TL;DR

This paper introduces an inorganic on-chip stencil lithography mask for superconducting qubit fabrication, enabling high-temperature processing and cleaner interfaces, demonstrated with Al-based transmon qubits.

Contribution

Development of a resilient inorganic SiO2/Si3N4 stencil mask for Josephson junction fabrication, compatible with high temperatures and aggressive cleaning, improving qubit interface quality.

Findings

Achieved average T1 of 75 ± 11 μs over 200 MHz in one device.

Achieved T1 of 44 ± 8 μs in a second device.

Demonstrated compatibility of stencil lithography with superconducting qubits.

Abstract

Improvements in circuit design and more recently in materials and surface cleaning have contributed to a rapid development of coherent superconducting qubits. However, organic resists commonly used for shadow evaporation of Josephson junctions (JJs) pose limitations due to residual contamination, poor thermal stability and compatibility under typical surface-cleaning conditions. To provide an alternative, we developed an inorganic SiO$_2$/Si$_3$N$_4$ on-chip stencil lithography mask for JJ fabrication. The stencil mask is resilient to aggressive cleaning agents and it withstands high temperatures up to 1200{\deg}C, thereby opening new avenues for JJ material exploration and interface optimization. To validate the concept, we performed shadow evaporation of Al-based transmon qubits followed by stencil mask lift-off using vapor hydrofluoric acid, which selectively etches SiO$_2$. We demonstrate average $T_1 \approx 75 \pm 11 \mu$s over a 200 MHz frequency range in multiple cool-downs for one device, and $T_1 \approx 44\pm 8 \mu$s for a second device. These results confirm the compatibility of stencil lithography with state-of-the-art superconducting quantum devices and motivate further investigations into materials engineering, film deposition and surface cleaning techniques.