PPAAS: PVT and Pareto Aware Analog Sizing via Goal-conditioned Reinforcement Learning
Seunggeun Kim, Ziyi Wang, Sungyoung Lee, Youngmin Oh, Hanqing Zhu, Doyun Kim, David Z. Pan

TL;DR
This paper introduces PPAAS, a goal-conditioned reinforcement learning framework for analog device sizing that efficiently handles PVT variations, achieving significant improvements in sample and simulation efficiency over existing methods.
Contribution
The paper presents a novel goal-conditioned RL approach with Pareto-front goal sampling and stabilization techniques for robust, efficient analog device sizing across PVT variations.
Findings
Achieves approximately 1.6x better sample efficiency.
Achieves approximately 4.1x better simulation efficiency.
Demonstrates effectiveness on benchmark circuits.
Abstract
Device sizing is a critical yet challenging step in analog and mixed-signal circuit design, requiring careful optimization to meet diverse performance specifications. This challenge is further amplified under process, voltage, and temperature (PVT) variations, which cause circuit behavior to shift across different corners. While reinforcement learning (RL) has shown promise in automating sizing for fixed targets, training a generalized policy that can adapt to a wide range of design specifications under PVT variations requires much more training samples and resources. To address these challenges, we propose a \textbf{Goal-conditioned RL framework} that enables efficient policy training for analog device sizing across PVT corners, with strong generalization capability. To improve sample efficiency, we introduce Pareto-front Dominance Goal Sampling, which constructs an automatic…
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Taxonomy
TopicsVLSI and FPGA Design Techniques · Low-power high-performance VLSI design · Physical Unclonable Functions (PUFs) and Hardware Security
