SVAgent: AI Agent for Hardware Security Verification Assertion

TL;DR

This paper introduces SVAgent, an automated framework for generating SystemVerilog assertions to improve hardware security verification, addressing limitations of traditional methods in complex circuit designs.

Contribution

SVAgent presents a novel requirement decomposition mechanism for efficient, accurate, and reliable assertion generation in hardware security verification.

Findings

Significantly improved accuracy and consistency of SVA

Effectively reduces hallucinations and random answers

Successfully integrated into mainstream vulnerability assessment frameworks

Abstract

Verification using SystemVerilog assertions (SVA) is one of the most popular methods for detecting circuit design vulnerabilities. However, with the globalization of integrated circuit design and the continuous upgrading of security requirements, the SVA development model has exposed major limitations. It is not only inefficient in development, but also unable to effectively deal with the increasing number of security vulnerabilities in modern complex integrated circuits. In response to these challenges, this paper proposes an innovative SVA automatic generation framework SVAgent. SVAgent introduces a requirement decomposition mechanism to transform the original complex requirements into a structured, gradually solvable fine-grained problem-solving chain. Experiments have shown that SVAgent can effectively suppress the influence of hallucinations and random answers, and the key evaluation indicators such as the accuracy and consistency of the SVA are significantly better than existing frameworks. More importantly, we successfully integrated SVAgent into the most mainstream integrated circuit vulnerability assessment framework and verified its practicality and reliability in a real engineering design environment.