RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

TL;DR

RealBench is a new benchmark for evaluating large language models' ability to generate complex, real-world IP-level Verilog code with rigorous verification, revealing current models' limited performance and highlighting the need for improvement.

Contribution

It introduces the first comprehensive benchmark with real-world IP designs, multi-modal specifications, and rigorous verification for Verilog generation tasks.

Findings

Best LLMs achieve only 13.3% pass@1 on module-level tasks.

Zero success rate on system-level tasks.

Highlights the gap between current LLM capabilities and real-world hardware design requirements.

Abstract

The automatic generation of Verilog code using Large Language Models (LLMs) has garnered significant interest in hardware design automation. However, existing benchmarks for evaluating LLMs in Verilog generation fall short in replicating real-world design workflows due to their designs' simplicity, inadequate design specifications, and less rigorous verification environments. To address these limitations, we present RealBench, the first benchmark aiming at real-world IP-level Verilog generation tasks. RealBench features complex, structured, real-world open-source IP designs, multi-modal and formatted design specifications, and rigorous verification environments, including 100% line coverage testbenches and a formal checker. It supports both module-level and system-level tasks, enabling comprehensive assessments of LLM capabilities. Evaluations on various LLMs and agents reveal that even one of the best-performing LLMs, o1-preview, achieves only a 13.3% pass@1 on module-level tasks and 0% on system-level tasks, highlighting the need for stronger Verilog generation models in the future. The benchmark is open-sourced at https://github.com/IPRC-DIP/RealBench.