VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair

TL;DR

VeriRAG is a novel retrieval-augmented framework utilizing LLMs for automated design-for-testability repairs in RTL code, significantly improving repair success rates.

Contribution

First LLM-assisted DFT-EDA framework employing retrieval-augmented generation and a new Verilog DFT dataset for automated RTL repair.

Findings

7.72-fold increase in successful repair rate over baseline

Effective retrieval of structurally similar RTL designs for repair

Open-sourced data, models, and scripts for reproducibility

Abstract

Large language models (LLMs) have demonstrated immense potential in computer-aided design (CAD), particularly for automated debugging and verification within electronic design automation (EDA) tools. However, Design for Testability (DFT) remains a relatively underexplored area. This paper presents VeriRAG, the first LLM-assisted DFT-EDA framework. VeriRAG leverages a Retrieval-Augmented Generation (RAG) approach to enable LLM to revise code to ensure DFT compliance. VeriRAG integrates (1) an autoencoder-based similarity measurement model for precise retrieval of reference RTL designs for the LLM, and (2) an iterative code revision pipeline that allows the LLM to ensure DFT compliance while maintaining synthesizability. To support VeriRAG, we introduce VeriDFT, a Verilog-based DFT dataset curated for DFT-aware RTL repairs. VeriRAG retrieves structurally similar RTL designs from VeriDFT, each paired with a rigorously validated correction, as references for code repair. With VeriRAG and VeriDFT, we achieve fully automated DFT correction -- resulting in a 7.72-fold improvement in successful repair rate compared to the zero-shot baseline (Fig. 5 in Section V). Ablation studies further confirm the contribution of each component of the VeriRAG framework. We open-source our data, models, and scripts at https://github.com/HarminChee/VeriRAG.