One Step Beyond: Feedthrough & Placement-Aware Rectilinear Floorplanner

TL;DR

This paper introduces Flora, a three-stage rectilinear floorplanner that optimizes wirelength, feedthrough, and component placement by integrating placement-aware strategies across stages, leading to significant improvements over existing methods.

Contribution

Flora is a novel three-stage floorplanning approach that jointly optimizes module shapes, feedthrough, and component placement with cross-stage feedback, enhancing overall chip PPA metrics.

Findings

Achieves 6% reduction in HPWL

Reduces FTpin by 5.16%

Improves component placement by 14%

Abstract

Floorplanning determines the shapes and locations of modules on a chip canvas and plays a critical role in optimizing the chip's Power, Performance, and Area (PPA) metrics. However, existing floorplanning approaches often fail to integrate with subsequent physical design stages, leading to suboptimal in-module component placement and excessive inter-module feedthrough. To tackle this challenge, we propose Flora, a three-stage feedthrough and placement aware rectilinear floorplanner. In the first stage, Flora employs wiremask and position mask techniques to achieve coarse-grained optimization of HPWL and feedthrough. In the second stage, under the constraint of a fixed outline, Flora achieves a zero-whitespace layout by locally resizing module shapes, thereby performing fine-grained optimization of feedthrough and improving component placement. In the third stage, Flora utilizes a fast tree search-based method to efficiently place components-including macros and standard cells-within each module, subsequently adjusting module boundaries based on the placement results to enable cross-stage optimization. Experimental results show that Flora outperforms recent state-of-the-art floorplanning approaches, achieving an average reduction of 6% in HPWL, 5.16% in FTpin, 29.15% in FTmod, and a 14% improvement in component placement performance.