VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs

TL;DR

VeriOpt introduces a role-based, PPA-aware prompting framework for LLMs to generate high-quality, synthesizable Verilog, significantly improving power, area, and timing metrics while maintaining functional correctness.

Contribution

This work presents a novel multi-role prompting approach with integrated PPA constraints, enabling LLMs to produce industry-grade Verilog designs with optimized PPA metrics.

Findings

Up to 88% power reduction

76% area reduction

73% timing improvement

Abstract

The rapid adoption of large language models(LLMs) in hardware design has primarily focused on generating functionally correct Verilog code, overlooking critical Power Performance-Area(PPA) metrics essential for industrial-grade designs. To bridge this gap, we propose VeriOpt, a novel framework that leverages role-based prompting and PPA-aware optimization to enable LLMs to produce high-quality, synthesizable Verilog. VeriOpt structures LLM interactions into specialized roles (e.g., Planner, Programmer, Reviewer, Evaluator) to emulate human design workflows, while integrating PPA constraints directly into the prompting pipeline. By combining multi-modal feedback (e.g., synthesis reports, timing diagrams) with PPA aware prompting, VeriOpt achieves PPA-efficient code generation without sacrificing functional correctness. Experimental results demonstrate up to 88% reduction in power, 76% reduction in area and 73% improvement in timing closure compared to baseline LLM-generated RTL, validated using industry standard EDA tools. At the same time achieves 86% success rate in functionality evaluation. Our work advances the state-of-the-art AI-driven hardware design by addressing the critical gap between correctness and quality, paving the way for reliable LLM adoption in production workflows.