Quantum Circuit Optimization Based on Dynamic Grouping and ZX-Calculus for Reducing 2-Qubit Gate Count

TL;DR

This paper introduces a novel quantum circuit optimization method that combines dynamic grouping, ZX-calculus, and simulated annealing to significantly reduce two-qubit gate counts, enhancing circuit efficiency in the NISQ era.

Contribution

It presents a new optimization approach integrating dynamic grouping, ZX-calculus, and iterative strategies to effectively minimize two-qubit gates in quantum circuits.

Findings

Achieves an average of 18% reduction in two-qubit gates.

Outperforms classical methods with up to 25% reduction.

Shows a 4% average improvement over heuristic ZX-calculus methods.

Abstract

In the noisy intermediate-scale quantum (NISQ) era, two-qubit gates in quantum circuits are more susceptible to noise than single-qubit gates. Therefore, reducing the number of two-qubit gates is crucial for improving circuit efficiency and reliability. As quantum circuits scale up, the optimization search space becomes increasingly complex, leading to challenges such as low efficiency and suboptimal solutions. To address these issues, this paper proposes a quantum circuit optimization approach based on dynamic grouping and ZX-calculus. First, a random strategy-based dynamic grouping method partitions the circuit into multiple subcircuits. Second, a ZX-calculus guided k-step lookahead search performs equivalent subcircuit filtering to minimize two-qubit gate counts. Third, a delay-aware placement method optimizes the recombined circuit to reduce the overall gate count. Finally, simulated annealing iteratively updates the grouping strategy to achieve an optimized two-qubit gate count. Experimental results on benchmark datasets demonstrate the effectiveness and superiority of the proposed method in reducing two-qubit gates. Compared to the original circuits, the approach achieves an average reduction of 18% in two-qubit gates. It outperforms classical methods with up to 25% reduction, especially on gf circuits, and shows a 4% average improvement over heuristic ZX-calculus-based methods, validating its efficiency.