4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation

TL;DR

This paper introduces a 4T2R ReRAM cell and an 8T SRAM-based computation-in-memory array that enhances variation tolerance and reduces errors, enabling low-power, high-speed, massively parallel MAC operations for AI accelerators.

Contribution

The paper proposes a novel 4T2R ReRAM cell and an 8T SRAM CiM architecture that improve variation tolerance and error reduction in high-parallelism MAC computations.

Findings

Reduced device variation errors with 4T2R ReRAM compared to 4T4R cells

Enhanced variation tolerance in the proposed CiM array

Potential for low-power, high-speed AI acceleration

Abstract

Computation-in-Memory (CiM) is attracting attention as a technology that can perform MAC calculations required for AI accelerators, at high speed with low power consumption. However, there is a problem regarding power consumption and device-derived errors that increase as row parallelism increases. In this paper, a 4T2R ReRAM cell and an 8T SRAM CiM suitable for CiM is proposed. It is shown that adopting the proposed 4T2R ReRAM cell reduces the errors due to variation in ReRAM devices compared to conventional 4T4R ReRAM cells.