Mapping diverse hysteresis dynamics in scaled MoS$_2$ FETs using the universal method derived from TCAD modeling
Yezhu Lv, Haihui Cai, Yehao Wu, Yu.Yu. Illarionov

TL;DR
This paper introduces a universal hysteresis mapping method for nanoscale MoS2 FETs using TCAD modeling, capturing complex hysteresis behaviors and their relation to bias-temperature instabilities, validated with experimental data.
Contribution
The paper presents a novel universal hysteresis mapping approach derived from TCAD modeling for scaled MoS2 FETs, improving accuracy over traditional methods.
Findings
The method accurately captures diverse hysteresis dynamics including CW, CCW, and switching behaviors.
A clear correlation between hysteresis dynamics and bias-temperature instability recovery is demonstrated.
Validation shows the method outperforms conventional hysteresis width extraction techniques.
Abstract
Field-effect transistors (FETs) based on 2D materials have already reached the stage of trial FAB integration. However, reliability limitations caused by various defects present a serious obstacle for their smooth way forward, especially when scaling the device geometries. Still the ongoing research is mostly focused on pure technology aspects, while reliability is often recalled only when showing a randomly measured gate transfer curve to manifest that the hysteresis is "negligible".In fact the hysteresis dynamics contain unique fingerprints of various mechanisms which may coexist or cancel each other, being more complex in scaled FETs, for instance because of simultaneous interaction of defects with the channel and top gate in thin insulators. To fill this gap, here by doing TCAD modeling for nanoscale MoS/HfO FETs we introduce the universal hysteresis mapping method which can…
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Taxonomy
TopicsAdvancements in Semiconductor Devices and Circuit Design · Ferroelectric and Negative Capacitance Devices
