Fine-grained Timing Analysis of Digital Integrated Circuits in Answer Set Programming

TL;DR

This paper presents a novel approach using Answer Set Programming to accurately compute maximum delays in integrated circuits, improving over traditional static timing analysis methods.

Contribution

It introduces new ASP encodings for maximum delay computation, enabling more precise timing analysis in hardware design.

Findings

ASP can effectively compute maximum delays in complex circuits.

The approach outperforms traditional static timing analysis in accuracy.

Experimental results demonstrate ASP's viability for hardware timing problems.

Abstract

In the design of integrated circuits, one critical metric is the maximum delay introduced by combinational modules within the circuit. This delay is crucial because it represents the time required to perform a computation: in an Arithmetic-Logic Unit it represents the maximum time taken by the circuit to perform an arithmetic operation. When such a circuit is part of a larger, synchronous system, like a CPU, the maximum delay directly impacts the maximum clock frequency of the entire system. Typically, hardware designers use Static Timing Analysis to compute an upper bound of the maximum delay because it can be determined in polynomial time. However, relying on this upper bound can lead to suboptimal processor speeds, thereby missing performance opportunities. In this work, we tackle the challenging task of computing the actual maximum delay, rather than an approximate value. Since the problem is computationally hard, we model it in Answer Set Programming (ASP), a logic language featuring extremely efficient solvers. We propose non-trivial encodings of the problem into ASP. Experimental results show that ASP is a viable solution to address complex problems in hardware design.