Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper
Cunxi Yu

TL;DR
This paper introduces FuseMap, a novel framework that leverages ASIC technology mapping techniques and reinforcement learning to enhance FPGA LUT mapping, resulting in improved accuracy, delay, and area efficiency.
Contribution
FuseMap integrates ASIC mapping strategies with FPGA LUT mapping using reinforcement learning, enabling incremental optimization and better performance in FPGA design flow.
Findings
Higher mapping accuracy achieved
Reduced delay and area in FPGA circuits
Effective across diverse benchmarks
Abstract
LUT (Look-Up Table) mapping is a critical step in FPGA logic synthesis, where a logic network is transformed into a form that can be directly implemented using the FPGA's LUTs. An FPGA LUT is a flexible digital memory structure that can implement any logic function of a limited number of inputs, typically 4 to 6 inputs, depending on the FPGA architecture. The goal of LUT mapping is to map the Boolean network into LUTs, where each LUT can implement any function with a fixed number of inputs. In parallel to FPGA technology mapping, ASIC technology mapping maps the Boolean network to user-defined standard cells, which has traditionally been developed separately from LUT mapping algorithms. However, in this work, our motivating examples demonstrate that ASIC technology mappers can potentially improve the performance of LUT mappers, such that standard cell mapping and LUT mapping work in an…
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Taxonomy
TopicsVLSI and Analog Circuit Testing · Embedded Systems Design Techniques · Integrated Circuits and Semiconductor Failure Analysis
