SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST

TL;DR

This paper presents SFATTI, a spiking FPGA accelerator optimized for temporal, task-driven inference, demonstrated through a case study on MNIST digit recognition, highlighting the benefits of SNNs on FPGA platforms.

Contribution

It introduces a methodology using the Spiker+ framework to generate optimized SNN accelerators for FPGA, focusing on low-power, low-latency edge inference.

Findings

Achieved efficient MNIST digit recognition with SNNs on FPGA.

Demonstrated trade-offs between accuracy, power, and latency.

Showcased the flexibility of Spiker+ for hardware design.

Abstract

Hardware accelerators are essential for achieving low-latency, energy-efficient inference in edge applications like image recognition. Spiking Neural Networks (SNNs) are particularly promising due to their event-driven and temporally sparse nature, making them well-suited for low-power Field Programmable Gate Array (FPGA)-based deployment. This paper explores using the open-source Spiker+ framework to generate optimized SNNs accelerators for handwritten digit recognition on the MNIST dataset. Spiker+ enables high-level specification of network topologies, neuron models, and quantization, automatically generating deployable HDL. We evaluate multiple configurations and analyze trade-offs relevant to edge computing constraints.