AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design

TL;DR

AnalogTester leverages large language models to automate testbench generation for analog circuits, reducing manual effort and enhancing flexibility in design automation.

Contribution

It introduces a novel LLM-based pipeline for automatic testbench creation in analog circuit design, including knowledge integration, information extraction, and code generation.

Findings

Successfully generated testbenches for op-amps, BGRs, and LDOs.

Established scalable framework adaptable to various circuit topologies.

Created datasets for training LLMs in analog circuit automation.

Abstract

Recent advancements have demonstrated the significant potential of large language models (LLMs) in analog circuit design. Nevertheless, testbench construction for analog circuits remains manual, creating a critical bottleneck in achieving fully automated design processes. Particularly when replicating circuit designs from academic papers, manual Testbench construction demands time-intensive implementation and frequent adjustments, which fails to address the dynamic diversity and flexibility requirements for automation. AnalogTester tackles automated analog design challenges through an LLM-powered pipeline: a) domain-knowledge integration, b) paper information extraction, c) simulation scheme synthesis, and d) testbench code generation with Tsinghua Electronic Design (TED). AnalogTester has demonstrated automated Testbench generation capabilities for three fundamental analog circuit types: operational amplifiers (op-amps), bandgap references (BGRs), and low-dropout regulators (LDOs), while maintaining a scalable framework for adaptation to broader circuit topologies. Furthermore, AnalogTester can generate circuit knowledge data and TED code corpus, establishing fundamental training datasets for LLM specialization in analog circuit design automation.