Compute SNR-Optimal Analog-to-Digital Converters for Analog In-Memory Computing
Mihir Kavishwar, Naresh Shanbhag

TL;DR
This paper introduces a new analytical method and algorithm for designing energy-efficient ADCs in analog in-memory computing, optimizing accuracy by precisely estimating the true signal-to-noise ratio.
Contribution
It develops a circuit-aware analytical model for CSNR and proposes CACTUS, an algorithm to design ADCs that meet accuracy targets with minimal precision, outperforming prior SQNR-based methods.
Findings
CACTUS reduces ADC precision by 3 bits for a 256-dimensional binary dot product.
Achieves 6dB higher CSNR compared to prior methods.
Outperforms conventional SQNR-optimal ADCs under certain conditions.
Abstract
Analog in-memory computing (AIMC) is an energy-efficient alternative to digital architectures for accelerating machine learning and signal processing workloads. However, its energy efficiency is limited by the high energy cost of the column analog-to-digital converters (ADCs). Reducing the ADC precision is an effective approach to lowering its energy cost. However, doing so also reduces the AIMC's computational accuracy thereby making it critical to identify the minimum precision required to meet a target accuracy. Prior works overestimate the ADC precision requirements by modeling quantization error as input-independent noise, maximizing the signal-to-quantization-noise ratio (SQNR), and ignoring the discrete nature of ideal pre-ADC signal. We address these limitations by developing analytical expressions for estimating the compute signal-to-noise ratio (CSNR), a true metric of…
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