Tools and Methodologies for System-Level Design
Shuvra S. Bhattacharyya, Marilyn Wolf

TL;DR
This paper reviews tools and methodologies for system-level design of SoCs, emphasizing modeling, simulation, and design space exploration to address the complexities of modern chip development.
Contribution
It provides a comprehensive overview of system-level design tools and methodologies, highlighting their roles in modeling, verification, and exploration for complex SoC development.
Findings
Modeling captures system semantics for implementation and verification.
Design space exploration aids in understanding trade-offs in hardware/software co-design.
Simulation verifies functionality and assesses performance and energy consumption.
Abstract
System-level design, once the province of board designers, has now become a central concern for chip designers. Because chip design is a less forgiving design medium -- design cycles are longer and mistakes are harder to correct -- system-on-chip designers need a more extensive tool suite than may be used by board designers and a variety of tools and methodologies have been developed for system-level design of systems-on-chips (SoCs). System-level design is less amenable to synthesis than are logic or physical design. As a result, system-level tools concentrate on modeling, simulation, design space exploration, and design verification. The goal of modeling is to correctly capture the system's operational semantics, which helps with both implementation and verification. The study of models of computation provides a framework for the description of digital systems. Not only do we need to…
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Taxonomy
TopicsEmbedded Systems Design Techniques
