Impedance-Engineered Josephson Parametric Amplifier with Single-Step Lithography

TL;DR

This paper demonstrates a simplified fabrication process for impedance-engineered Josephson parametric amplifiers, achieving high gain, wide bandwidth, and near-quantum-limited noise performance, supported by extended theoretical modeling.

Contribution

It introduces a single-step lithography fabrication method for impedance-engineered JPAs and extends existing theories to include full sine nonlinearity effects.

Findings

18 dB gain over 400 MHz bandwidth

Approaching quantum-limited noise performance

Saturation power of -114 dBm

Abstract

We present the experimental demonstration of an impedance-engineered Josephson parametric amplifier (IEJPA) fabricated in a single-step lithography process. Impedance engineering is implemented using a lumped-element series LC circuit. We use a simpler lithography process where the entire device -- impedance transformer and JPA -- are patterned in a single electron beam lithography step, followed by a double-angle Dolan bridge technique for Al-AlO$_x$-Al deposition. We observe amplification with 18 dB gain over a wide $400\,$MHz bandwidth centered around $5.3$GHz with added noise approaching the quantum limit, and a saturation power of $-114$dBm. To accurately explain our experimental results, we extend existing theories for impedance-engineered JPAs to incorporate the full sine nonlinearity of both the JPA and the transformer. Our work shows a path to simpler realization of broadband JPAs and provides a theoretical foundation for a regime of JPA operation that has been less explored in literature.