Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs

TL;DR

This paper introduces a deep learning model combining GNN and MLP to accurately predict parasitic capacitances in SRAM pre-layout designs, significantly improving prediction accuracy and simulation speed.

Contribution

It presents a novel 2-stage deep learning model that effectively manages class imbalance and hierarchical circuit structure for parasitic prediction in SRAM designs.

Findings

Achieves up to 19X reduction in prediction error.

Provides up to 598X speedup in simulation process.

Outperforms existing models in accuracy and efficiency.

Abstract

To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulations, leading to difficulty in converging design parameters and excessive design iterations. Is it possible to well predict the parasitics based on the pre-layout circuit, so as to perform parasitic-aware pre-layout simulation? In this work, we propose a deep-learning-based 2-stage model to accurately predict these parasitics in pre-layout stages. The model combines a Graph Neural Network (GNN) classifier and Multi-Layer Perceptron (MLP) regressors, effectively managing class imbalance of the net parasitics in SRAM circuits. We also employ Focal Loss to mitigate the impact of abundant internal net samples and integrate subcircuit information into the graph to abstract the hierarchical structure of schematics. Experiments on 4 real SRAM designs show that our approach not only surpasses the state-of-the-art model in parasitic prediction by a maximum of 19X reduction of error but also significantly boosts the simulation process by up to 598X speedup.