GATMesh: Clock Mesh Timing Analysis using Graph Neural Networks

TL;DR

GATMesh uses graph neural networks to accurately and rapidly analyze clock mesh timing in VLSI systems, significantly outperforming traditional SPICE simulations in speed while maintaining high accuracy.

Contribution

This paper introduces GATMesh, a novel GNN-based framework that models clock meshes for fast and precise timing analysis, capturing effects like slew and input skew.

Findings

Achieves 5.27ps average delay error on unseen benchmarks.

Provides 47146x speed-up over multi-threaded SPICE simulation.

Effectively models complex clock mesh behaviors with GNNs.

Abstract

Clock meshes are essential in high-performance VLSI systems for minimizing skew and handling PVT variations, but analyzing them is difficult due to reconvergent paths, multi-source driving, and input mesh buffer skew. SPICE simulations are accurate but slow; yet simplified models miss key effects like slew and input skew. We propose GATMesh, a Graph Neural Network (GNN)-based framework that models the clock mesh as a graph with augmented structural and physical features. Trained on SPICE data, GATMesh achieves high accuracy with average delay error of 5.27ps on unseen benchmarks, while achieving speed-ups of 47146x over multi-threaded SPICE simulation.