Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads

TL;DR

This paper provides the first real hardware performance analysis of Per-Row Activation Counting (PRAC), revealing significantly lower overheads than previous simulator-based estimates, and highlights the effectiveness of the close page policy in mitigating delays.

Contribution

It offers the first real-machine performance evaluation of PRAC, demonstrating lower overheads and the impact of page policies on performance.

Findings

PRAC overheads are only 1.06% on average for SPEC CPU2017.

Maximum overhead observed is 3.28%, much lower than prior estimates.

Close page policy effectively minimizes PRAC-induced delays.

Abstract

Per-Row Activation Counting (PRAC), a DRAM read disturbance mitigation method, modifies key DRAM timing parameters, reportedly causing significant performance overheads in simulator-based studies. However, given known discrepancies between simulators and real hardware, real-machine experiments are vital for accurate PRAC performance estimation. We present the first real-machine performance analysis of PRAC. After verifying timing modifications on the latest CPUs using microbenchmarks, our analysis shows that PRAC's average and maximum overheads are just 1.06% and 3.28% for the SPEC CPU2017 workloads -- up to 9.15x lower than simulator-based reports. Further, we show that the close page policy minimizes this overhead by effectively hiding the elongated DRAM row precharge operations due to PRAC from the critical path.