Voltage Mode Winner-Take-All Circuit for Neuromorphic Systems

TL;DR

This paper introduces a configurable winner-take-all circuit for neuromorphic systems, demonstrating low power consumption, fast processing, and applicability to spatial filtering and classification tasks.

Contribution

A novel winner-take-all circuit with k-winner and hysteresis features, simulated in 65 nm technology, advancing neuromorphic hardware capabilities.

Findings

Power dissipation of 34.9 μW

Latency of 10.4 ns for 1000 inputs

Effective in spatial filtering and classification

Abstract

Recent advances in neuromorphic computing demonstrate on-device learning capabilities with low power consumption. One of the key learning units in these systems is the winner-take-all circuit. In this research, we propose a winner-take-all circuit that can be configured to achieve k-winner and hysteresis properties, simulated in IBM 65 nm node. The circuit dissipated 34.9 $\mu$W of power with a latency of 10.4 ns, while processing 1000 inputs. The utility of the circuit is demonstrated for spatial filtering and classification.