In-Network Memory Access: Bridging SmartNIC and Host Memory

TL;DR

This paper evaluates various methods for enabling efficient memory access between SmartNICs and host memory, addressing communication challenges to improve in-network application performance.

Contribution

It provides a comprehensive analysis of memory access performance techniques for SmartNICs, guiding optimal design choices for in-network systems.

Findings

Different memory access approaches have varying performance impacts.

Performance analysis supports selecting suitable memory access designs.

Insights help optimize SmartNIC and host memory communication.

Abstract

SmartNICs have been increasingly utilized across various applications to offload specific computational tasks, thereby enhancing overall system performance. However, this offloading process introduces several communication challenges that must be addressed for effective integration. A key challenge lies in establishing efficient communication between the offloaded components and the main application running on the host. In this study, we evaluate different approaches for achieving memory access between the host and SmartNIC. We analyze memory access performance on both the SmartNIC and the host to support in-network applications and guide the selection of an appropriate memory access design.