Effective Capacitance Modeling Using Graph Neural Networks

TL;DR

This paper introduces GNN-Ceff, a graph neural network-based method for fast and accurate effective capacitance modeling in VLSI timing analysis, leveraging GPU parallelization for significant speed improvements.

Contribution

It presents the first GNN-based approach for post-layout effective capacitance modeling, achieving higher accuracy and much faster computation than existing heuristics.

Findings

GNN-Ceff achieves 929x speedup over traditional methods.

GNN-Ceff provides better accuracy than current heuristics.

The method leverages GPU parallelization for efficiency.

Abstract

Static timing analysis is a crucial stage in the VLSI design flow that verifies the timing correctness of circuits. Timing analysis depends on the placement and routing of the design, but at the same time, placement and routing efficiency depend on the final timing performance. VLSI design flows can benefit from timing-related prediction to better perform the earlier stages of the design flow. Effective capacitance is an essential input for gate delay calculation, and finding exact values requires routing or routing estimates. In this work, we propose the first GNN-based post-layout effective capacitance modeling method, GNN-Ceff, that achieves significant speed gains due to GPU parallelization while also providing better accuracy than current heuristics. GNN-Ceff parallelization achieves 929x speedup on real-life benchmarks over the state-of-the-art method run serially.