Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification

TL;DR

This paper introduces an agentic AI approach for hardware design and verification, leveraging Large Language Models and human-in-the-loop collaboration to improve efficiency, coverage, and adaptability in complex IC development.

Contribution

It proposes a novel AI-based methodology for hardware verification that combines autonomous AI agents with human oversight, enabling end-to-end design and faster, more comprehensive verification.

Findings

Achieved over 95% verification coverage on five open-source designs.

Reduced verification time compared to traditional methods.

Demonstrated superior adaptability and configurability of the AI system.

Abstract

Modern Integrated Circuits (ICs) are becoming increasingly complex, and so is their development process. Hardware design verification entails a methodical and disciplined approach to the planning, development, execution, and sign-off of functionally correct hardware designs. This tedious process requires significant effort and time to ensure a bug-free tape-out. The field of Natural Language Processing has undergone a significant transformation with the advent of Large Language Models (LLMs). These powerful models, often referred to as Generative AI (GenAI), have revolutionized how machines understand and generate human language, enabling unprecedented advancements in a wide array of applications, including hardware design verification. This paper presents an agentic AI-based approach to hardware design verification, which empowers AI agents, in collaboration with Humain-in-the-Loop (HITL) intervention, to engage in a more dynamic, iterative, and self-reflective process, ultimately performing end-to-end hardware design and verification. This methodology is evaluated on five open-source designs, achieving over 95% coverage with reduced verification time while demonstrating superior performance, adaptability, and configurability.