The impact of process steps on nearly ideal subthreshold slope in 300-mm compatible InGaZnO TFT
Hongwei Tang, Dennis Lin, Subhali Subhechha, Adrian Chasin, Daisuke Matsubayashi, Michiel van Setten, Yiqun Wan, Harold Dekkers, Jie Li, Shruthi Subramanian, Zhuo Chen, Nouredine Rassoul, Yuchao Jiang, Jan Van Houdt, Valeri Afanas`ev, Gouri Sankar Kar, and Attilio Belmonte
TL;DR
This study investigates how different process steps affect the subthreshold slope in InGaZnO TFTs, revealing hydrogen's role in SS deterioration through detailed measurements and annealing experiments.
Contribution
It identifies the impact of process steps and hydrogen incorporation on SS degradation in InGaZnO transistors, providing insights for optimizing fabrication.
Findings
Back-gated a-IGZO transistors achieve nearly ideal SS ~ 60 mV/dec.
Top-gated devices show degraded SS due to higher trap density.
Forming gas anneal reduces trap density and improves SS.
Abstract
While we demonstrate a back-gated (BG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) transistors with a nearly ideal subthreshold slope (SS) ~ 60 mV/dec. However, SS degrades when a top-gated (TG) configuration is implemented. The energy distribution of traps inferred from temperature-dependent (T = 4 K - 300 K) and multi-frequency (f = 1 kHz - 100 kHz) admittance measurements, reveals a much higher trap density in TG devices. By analyzing the impact of each process step and conducting forming gas anneal (FGA) experiments, we reveal the role of hydrogen in the deterioration of the SS in the IGZO-based transistors.
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