Adiabatic Capacitive Neuron: An Energy-Efficient Functional Unit for Artificial Neural Networks
Sachin Maheshwari, Mike Smart, Himadri Singh Raghav, Themis Prodromakis, Alexander Serb

TL;DR
This paper presents an energy-efficient Adiabatic Capacitive Neuron (ACN) hardware implementation that significantly reduces energy consumption while maintaining accuracy, robustness, and scalability in artificial neural network applications.
Contribution
The paper introduces a novel ACN hardware design with a new threshold logic for binary activation, achieving over 90% energy savings compared to traditional CMOS neurons.
Findings
Maximum offset voltage of 9mV across process and temperature.
Over 90% energy savings in synapse energy compared to non-adiabatic CMOS neurons.
Consistent energy savings above 90% with supply voltage scaling.
Abstract
This paper introduces a new, highly energy-efficient, Adiabatic Capacitive Neuron (ACN) hardware implementation of an Artificial Neuron (AN) with improved functionality, accuracy, robustness and scalability over previous work. The paper describes the implementation of a \mbox{12-bit} single neuron, with positive and negative weight support, in an CMOS technology. The paper also presents a new Threshold Logic (TL) design for a binary AN activation function that generates a low symmetrical offset across three process corners and five temperatures between C and C. Post-layout simulations demonstrate a maximum rising and falling offset voltage of 9 compared to conventional TL, which has rising and falling offset voltages of 27 and 5 respectively, across temperature and process. Moreover, the proposed TL design shows a decrease in average energy…
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