Real-Time In-Network Machine Learning on P4-Programmable FPGA SmartNICs with Fixed-Point Arithmetic and Taylor

TL;DR

This paper demonstrates how P4-programmable FPGA SmartNICs can efficiently run in-network machine learning models like neural networks and regression, enabling low-latency, flexible, and retrainable ML inference directly at the network edge.

Contribution

It introduces a novel approach to implement neural networks and regression models on P4-programmable FPGA SmartNICs using control plane table lookups for weights and biases.

Findings

Enables low-latency ML inference at the network edge.

Supports dynamic reconfiguration and retraining of models.

Integrates ML models seamlessly with network packet processing.

Abstract

As machine learning (ML) applications become integral to modern network operations, there is an increasing demand for network programmability that enables low-latency ML inference for tasks such as Quality of Service (QoS) prediction and anomaly detection in cybersecurity. ML models provide adaptability through dynamic weight adjustments, making Programming Protocol-independent Packet Processors (P4)-programmable FPGA SmartNICs an ideal platform for investigating In-Network Machine Learning (INML). These devices offer high-throughput, low-latency packet processing and can be dynamically reconfigured via the control plane, allowing for flexible integration of ML models directly at the network edge. This paper explores the application of the P4 programming paradigm to neural networks and regression models, where weights and biases are stored in control plane table lookups. This approach enables flexible programmability and efficient deployment of retrainable ML models at the network edge, independent of core infrastructure at the switch level.