Presto: Hardware Acceleration of Ciphers for Hybrid Homomorphic Encryption

TL;DR

This paper presents FPGA-based hardware accelerators for two symmetric ciphers used in hybrid homomorphic encryption, significantly improving throughput, latency, and energy efficiency over software implementations.

Contribution

It introduces novel FPGA designs for HERA and Rubato ciphers, optimizing performance and energy consumption in hybrid homomorphic encryption systems.

Findings

6x throughput improvement over software

Rubato latency reduced by 5x

Energy consumption decreased by over 47x

Abstract

Hybrid Homomorphic Encryption (HHE) combines symmetric key and homomorphic encryption to reduce ciphertext expansion crucial in client-server deployments of HE. Special symmetric ciphers, amenable to efficient HE evaluation, have been developed. Their client-side deployment calls for performant and energy-efficient implementation, and in this paper we develop and evaluate hardware accelerators for the two known CKKS-targeting HHE ciphers, HERA and Rubato. We design vectorized and overlapped functional modules. The design exploits transposition-invariance property of the MixColumns and MixRows function and alternates the order of intermediate state to eliminate bubbles in stream key generation, improving latency and throughput. We decouple the RNG and key computation phases to hide the latency of RNG and to reduce the critical path in FIFOs, achieving higher operating frequency. We implement the accelerator on an AMD Virtex UltraScale+ FPGA. Both Rubato and HERA achieve a 6x improvement in throughput compared to the software implementation. In terms of latency, Rubato achieves a 5x reduction, while HERA achieves a 3x reduction. Additionally, our hardware implementations reduce energy consumption by 75x for Rubato and 47x for HERA compared to their software implementation.