An AST-guided LLM Approach for SVRF Code Synthesis

TL;DR

This paper presents a novel AST-guided LLM approach integrating retrieval-augmented generation for accurate SVRF code synthesis, addressing complexity and expertise gaps in semiconductor design rule development.

Contribution

It introduces a new methodology combining AST embedding and RAG with a specialized scoring framework for improved SVRF code generation accuracy.

Findings

Up to 40% improvement in code accuracy over baseline models.

Effective structural validation via AST enhances semantic correctness.

Method reduces manual errors and accelerates design cycle iterations.

Abstract

Standard Verification Rule Format (SVRF) is essential for semiconductor applications like Design Rule Check (DRC), Layout Versus Schematic (LVS), and Optical Proximity Correction (OPC) and it faces challenges as advancing nodes create complex design rules that renders traditional SVRF development ineffective and highlight an expertise gap. This paper introduces a novel methodology integrating Abstract Syntax Tree (AST) embedding and Retrieval-Augmented Generation (RAG) for enhanced SVRF code synthesis, ensuring semantic accuracy and error minimization through structural validation with domain-specific insights for precise code generation. We evaluate different T5-based models and propose an innovative SVRF-specific scoring framework that complements standard metrics like BLEU and ROUGE-L. In our approach, AST provides rigorous structural validation, while RAG infuses relevant domain knowledge, effectively enhancing the code generation workflow. Testing on a comprehensive benchmark of 740 DRC rule implementations, our methodology demonstrates up to a 40\% improvement in code generation accuracy compared to basic text-based fine-tuning process. This fusion of industry expertise with advanced coding strategies not only optimizes SVRF development under limited dataset constraints but also creates a more intuitive and efficient coding environment. Consequently, users can rapidly iterate through design cycles, reduce manual error correction, and significantly improve overall productivity.