Stateful Logic In-Memory Using Gain-Cell eDRAM

TL;DR

This paper introduces a novel use of Gain-Cell eDRAM for in-memory logic, leveraging its dual-port and nondestructive read features to perform logic operations directly within memory arrays, enhancing efficiency for data-heavy tasks.

Contribution

It presents a new circuit design for GC-eDRAM that enables in-memory logic functions, demonstrating improved density and power efficiency over traditional memory technologies.

Findings

Achieved 5 microsecond retention time with high logic success rate

Demonstrated enhanced memory and compute density with lower power consumption

Showed feasibility of in-memory logic operations using GC-eDRAM in simulations

Abstract

Modern data-intensive applications demand memory solutions that deliver high-density, low-power, and integrated computational capabilities to reduce data movement overhead. This paper presents the use of Gain-Cell embedded DRAM (GC-eDRAM) - a compelling alternative to traditional SRAM and eDRAM - for stateful, in-memory logic. We propose a circuit design that exploits GC-eDRAM's dual-port architecture and nondestructive read operation to perform logic functions directly within the GC-eDRAM memory array. Our simulation results demonstrate a 5us retention time coupled with a 99.5% success rate for computing the logic gates. By incorporating processing-in-memory (PIM) functionality into GC-eDRAM, our approach enhances memory and compute densities, lowers power consumption, and improves overall performance for data-intensive applications.